This guarantee the correct operation of an RS-Latch
In this circuit, S and R can never be 0 at the same time!
Q takes the value of D, when write enable (WE) is set to 1
extremely expensive: 18 transistors
<8Bits>
PRE: preset to 1 CLR: clear to 0
Problem: Transparency
We need to store the data at the beginning of every clock cycle
and the data must be available during the entire clock cycle
see Finite State Machine
When we set EN to high, the latch is transparent: the latch propagates D to Q
We want:
The solution is to use D flip flop